1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 /* All Rights Reserved */
27
28 #include <sys/param.h>
29 #include <sys/types.h>
30 #include <sys/vmparam.h>
31 #include <sys/systm.h>
32 #include <sys/signal.h>
33 #include <sys/stack.h>
34 #include <sys/regset.h>
35 #include <sys/privregs.h>
36 #include <sys/frame.h>
37 #include <sys/proc.h>
38 #include <sys/psw.h>
39 #include <sys/siginfo.h>
40 #include <sys/cpuvar.h>
41 #include <sys/asm_linkage.h>
42 #include <sys/kmem.h>
43 #include <sys/errno.h>
44 #include <sys/bootconf.h>
45 #include <sys/archsystm.h>
46 #include <sys/debug.h>
47 #include <sys/elf.h>
48 #include <sys/spl.h>
49 #include <sys/time.h>
50 #include <sys/atomic.h>
51 #include <sys/sysmacros.h>
52 #include <sys/cmn_err.h>
53 #include <sys/modctl.h>
54 #include <sys/kobj.h>
55 #include <sys/panic.h>
56 #include <sys/reboot.h>
57 #include <sys/time.h>
58 #include <sys/fp.h>
59 #include <sys/x86_archext.h>
60 #include <sys/auxv.h>
61 #include <sys/auxv_386.h>
62 #include <sys/dtrace.h>
63 #include <sys/brand.h>
64 #include <sys/machbrand.h>
65 #include <sys/cmn_err.h>
66
67 extern const struct fnsave_state x87_initial;
68 extern const struct fxsave_state sse_initial;
69
70 /*
71 * Map an fnsave-formatted save area into an fxsave-formatted save area.
72 *
73 * Most fields are the same width, content and semantics. However
74 * the tag word is compressed.
75 */
76 static void
77 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
78 {
79 uint_t i, tagbits;
80
81 fx->fx_fcw = fn->f_fcw;
82 fx->fx_fsw = fn->f_fsw;
83
84 /*
85 * copy element by element (because of holes)
86 */
87 for (i = 0; i < 8; i++)
88 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
89 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
90
91 /*
92 * synthesize compressed tag bits
93 */
94 fx->fx_fctw = 0;
95 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
96 if ((tagbits & 3) != 3)
97 fx->fx_fctw |= (1 << i);
98
99 fx->fx_fop = fn->f_fop;
100
101 #if defined(__amd64)
102 fx->fx_rip = (uint64_t)fn->f_eip;
103 fx->fx_rdp = (uint64_t)fn->f_dp;
104 #else
105 fx->fx_eip = fn->f_eip;
106 fx->fx_cs = fn->f_cs;
107 fx->__fx_ign0 = 0;
108 fx->fx_dp = fn->f_dp;
109 fx->fx_ds = fn->f_ds;
110 fx->__fx_ign1 = 0;
111 #endif
112 }
113
114 /*
115 * Map from an fxsave-format save area to an fnsave-format save area.
116 */
117 static void
118 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
119 {
120 uint_t i, top, tagbits;
121
122 fn->f_fcw = fx->fx_fcw;
123 fn->__f_ign0 = 0;
124 fn->f_fsw = fx->fx_fsw;
125 fn->__f_ign1 = 0;
126
127 top = (fx->fx_fsw & FPS_TOP) >> 11;
128
129 /*
130 * copy element by element (because of holes)
131 */
132 for (i = 0; i < 8; i++)
133 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
134 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
135
136 /*
137 * synthesize uncompressed tag bits
138 */
139 fn->f_ftw = 0;
140 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
141 uint_t ibit, expo;
142 const uint16_t *fpp;
143 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
144
145 if ((tagbits & 1) == 0) {
146 fn->f_ftw |= 3 << (i << 1); /* empty */
147 continue;
148 }
149
150 /*
151 * (tags refer to *physical* registers)
152 */
153 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
154 ibit = fpp[3] >> 15;
155 expo = fpp[4] & 0x7fff;
156
157 if (ibit && expo != 0 && expo != 0x7fff)
158 continue; /* valid fp number */
159
160 if (bcmp(fpp, &zero, sizeof (zero)))
161 fn->f_ftw |= 2 << (i << 1); /* NaN */
162 else
163 fn->f_ftw |= 1 << (i << 1); /* fp zero */
164 }
165
166 fn->f_fop = fx->fx_fop;
167
168 fn->__f_ign2 = 0;
169 #if defined(__amd64)
170 fn->f_eip = (uint32_t)fx->fx_rip;
171 fn->f_cs = U32CS_SEL;
172 fn->f_dp = (uint32_t)fx->fx_rdp;
173 fn->f_ds = UDS_SEL;
174 #else
175 fn->f_eip = fx->fx_eip;
176 fn->f_cs = fx->fx_cs;
177 fn->f_dp = fx->fx_dp;
178 fn->f_ds = fx->fx_ds;
179 #endif
180 fn->__f_ign3 = 0;
181 }
182
183 /*
184 * Map from an fpregset_t into an fxsave-format save area
185 */
186 static void
187 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
188 {
189 #if defined(__amd64)
190 bcopy(fp, fx, sizeof (*fx));
191 #else
192 const struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state;
193
194 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
195 fx->fx_mxcsr = fc->mxcsr;
196 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
197 #endif
198 /*
199 * avoid useless #gp exceptions - mask reserved bits
200 */
201 fx->fx_mxcsr &= sse_mxcsr_mask;
202 }
203
204 /*
205 * Map from an fxsave-format save area into a fpregset_t
206 */
207 static void
208 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
209 {
210 #if defined(__amd64)
211 bcopy(fx, fp, sizeof (*fx));
212 #else
213 struct fpchip_state *fc = &fp->fp_reg_set.fpchip_state;
214
215 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
216 fc->mxcsr = fx->fx_mxcsr;
217 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
218 #endif
219 }
220
221 #if defined(_SYSCALL32_IMPL)
222 static void
223 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
224 {
225 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
226
227 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
228 /*
229 * avoid useless #gp exceptions - mask reserved bits
230 */
231 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
232 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
233 }
234
235 static void
236 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
237 {
238 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
239
240 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
241 fc->mxcsr = fx->fx_mxcsr;
242 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
243 }
244
245 static void
246 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
247 {
248 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
249 dst->fp_reg_set.fpchip_state.status =
250 src->fp_reg_set.fpchip_state.status;
251 dst->fp_reg_set.fpchip_state.xstatus =
252 src->fp_reg_set.fpchip_state.xstatus;
253 }
254
255 static void
256 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
257 {
258 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
259 dst->fp_reg_set.fpchip_state.status =
260 src->fp_reg_set.fpchip_state.status;
261 dst->fp_reg_set.fpchip_state.xstatus =
262 src->fp_reg_set.fpchip_state.xstatus;
263 }
264 #endif
265
266 /*
267 * Set floating-point registers from a native fpregset_t.
268 */
269 void
270 setfpregs(klwp_t *lwp, fpregset_t *fp)
271 {
272 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
273
274 if (fpu->fpu_flags & FPU_EN) {
275 if (!(fpu->fpu_flags & FPU_VALID)) {
276 /*
277 * FPU context is still active, release the
278 * ownership.
279 */
280 fp_free(fpu, 0);
281 }
282 }
283 /*
284 * Else: if we are trying to change the FPU state of a thread which
285 * hasn't yet initialized floating point, store the state in
286 * the pcb and indicate that the state is valid. When the
287 * thread enables floating point, it will use this state instead
288 * of the default state.
289 */
290
291 switch (fp_save_mech) {
292 #if defined(__i386)
293 case FP_FNSAVE:
294 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn,
295 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn));
296 break;
297 #endif
298 case FP_FXSAVE:
299 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx);
300 fpu->fpu_regs.kfpu_xstatus =
301 fp->fp_reg_set.fpchip_state.xstatus;
302 break;
303
304 case FP_XSAVE:
305 fpregset_to_fxsave(fp,
306 &fpu->fpu_regs.kfpu_u.kfpu_xs.xs_fxsave);
307 fpu->fpu_regs.kfpu_xstatus =
308 fp->fp_reg_set.fpchip_state.xstatus;
309 fpu->fpu_regs.kfpu_u.kfpu_xs.xs_xstate_bv |=
310 (XFEATURE_LEGACY_FP | XFEATURE_SSE);
311 break;
312 default:
313 panic("Invalid fp_save_mech");
314 /*NOTREACHED*/
315 }
316
317 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status;
318 fpu->fpu_flags |= FPU_VALID;
319 }
320
321 /*
322 * Get floating-point registers into a native fpregset_t.
323 */
324 void
325 getfpregs(klwp_t *lwp, fpregset_t *fp)
326 {
327 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
328
329 kpreempt_disable();
330 if (fpu->fpu_flags & FPU_EN) {
331 /*
332 * If we have FPU hw and the thread's pcb doesn't have
333 * a valid FPU state then get the state from the hw.
334 */
335 if (fpu_exists && ttolwp(curthread) == lwp &&
336 !(fpu->fpu_flags & FPU_VALID))
337 fp_save(fpu); /* get the current FPU state */
338 }
339
340 /*
341 * There are 3 possible cases we have to be aware of here:
342 *
343 * 1. FPU is enabled. FPU state is stored in the current LWP.
344 *
345 * 2. FPU is not enabled, and there have been no intervening /proc
346 * modifications. Return initial FPU state.
347 *
348 * 3. FPU is not enabled, but a /proc consumer has modified FPU state.
349 * FPU state is stored in the current LWP.
350 */
351 if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) {
352 /*
353 * Cases 1 and 3.
354 */
355 switch (fp_save_mech) {
356 #if defined(__i386)
357 case FP_FNSAVE:
358 bcopy(&fpu->fpu_regs.kfpu_u.kfpu_fn, fp,
359 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn));
360 break;
361 #endif
362 case FP_FXSAVE:
363 fxsave_to_fpregset(&fpu->fpu_regs.kfpu_u.kfpu_fx, fp);
364 fp->fp_reg_set.fpchip_state.xstatus =
365 fpu->fpu_regs.kfpu_xstatus;
366 break;
367 case FP_XSAVE:
368 fxsave_to_fpregset(
369 &fpu->fpu_regs.kfpu_u.kfpu_xs.xs_fxsave, fp);
370 fp->fp_reg_set.fpchip_state.xstatus =
371 fpu->fpu_regs.kfpu_xstatus;
372 break;
373 default:
374 panic("Invalid fp_save_mech");
375 /*NOTREACHED*/
376 }
377 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
378 } else {
379 /*
380 * Case 2.
381 */
382 switch (fp_save_mech) {
383 #if defined(__i386)
384 case FP_FNSAVE:
385 bcopy(&x87_initial, fp, sizeof (x87_initial));
386 break;
387 #endif
388 case FP_FXSAVE:
389 case FP_XSAVE:
390 /*
391 * For now, we don't have any AVX specific field in ABI.
392 * If we add any in the future, we need to initial them
393 * as well.
394 */
395 fxsave_to_fpregset(&sse_initial, fp);
396 fp->fp_reg_set.fpchip_state.xstatus =
397 fpu->fpu_regs.kfpu_xstatus;
398 break;
399 default:
400 panic("Invalid fp_save_mech");
401 /*NOTREACHED*/
402 }
403 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
404 }
405 kpreempt_enable();
406 }
407
408 #if defined(_SYSCALL32_IMPL)
409
410 /*
411 * Set floating-point registers from an fpregset32_t.
412 */
413 void
414 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
415 {
416 fpregset_t fpregs;
417
418 fpregset_32ton(fp, &fpregs);
419 setfpregs(lwp, &fpregs);
420 }
421
422 /*
423 * Get floating-point registers into an fpregset32_t.
424 */
425 void
426 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
427 {
428 fpregset_t fpregs;
429
430 getfpregs(lwp, &fpregs);
431 fpregset_nto32(&fpregs, fp);
432 }
433
434 #endif /* _SYSCALL32_IMPL */
435
436 /*
437 * Return the general registers
438 */
439 void
440 getgregs(klwp_t *lwp, gregset_t grp)
441 {
442 struct regs *rp = lwptoregs(lwp);
443 #if defined(__amd64)
444 struct pcb *pcb = &lwp->lwp_pcb;
445 int thisthread = lwptot(lwp) == curthread;
446
447 grp[REG_RDI] = rp->r_rdi;
448 grp[REG_RSI] = rp->r_rsi;
449 grp[REG_RDX] = rp->r_rdx;
450 grp[REG_RCX] = rp->r_rcx;
451 grp[REG_R8] = rp->r_r8;
452 grp[REG_R9] = rp->r_r9;
453 grp[REG_RAX] = rp->r_rax;
454 grp[REG_RBX] = rp->r_rbx;
455 grp[REG_RBP] = rp->r_rbp;
456 grp[REG_R10] = rp->r_r10;
457 grp[REG_R11] = rp->r_r11;
458 grp[REG_R12] = rp->r_r12;
459 grp[REG_R13] = rp->r_r13;
460 grp[REG_R14] = rp->r_r14;
461 grp[REG_R15] = rp->r_r15;
462 grp[REG_FSBASE] = pcb->pcb_fsbase;
463 grp[REG_GSBASE] = pcb->pcb_gsbase;
464 if (thisthread)
465 kpreempt_disable();
466 if (pcb->pcb_rupdate == 1) {
467 grp[REG_DS] = pcb->pcb_ds;
468 grp[REG_ES] = pcb->pcb_es;
469 grp[REG_FS] = pcb->pcb_fs;
470 grp[REG_GS] = pcb->pcb_gs;
471 } else {
472 grp[REG_DS] = rp->r_ds;
473 grp[REG_ES] = rp->r_es;
474 grp[REG_FS] = rp->r_fs;
475 grp[REG_GS] = rp->r_gs;
476 }
477 if (thisthread)
478 kpreempt_enable();
479 grp[REG_TRAPNO] = rp->r_trapno;
480 grp[REG_ERR] = rp->r_err;
481 grp[REG_RIP] = rp->r_rip;
482 grp[REG_CS] = rp->r_cs;
483 grp[REG_SS] = rp->r_ss;
484 grp[REG_RFL] = rp->r_rfl;
485 grp[REG_RSP] = rp->r_rsp;
486 #else
487 bcopy(&rp->r_gs, grp, sizeof (gregset_t));
488 #endif
489 }
490
491 #if defined(_SYSCALL32_IMPL)
492
493 void
494 getgregs32(klwp_t *lwp, gregset32_t grp)
495 {
496 struct regs *rp = lwptoregs(lwp);
497 struct pcb *pcb = &lwp->lwp_pcb;
498 int thisthread = lwptot(lwp) == curthread;
499
500 if (thisthread)
501 kpreempt_disable();
502 if (pcb->pcb_rupdate == 1) {
503 grp[GS] = (uint16_t)pcb->pcb_gs;
504 grp[FS] = (uint16_t)pcb->pcb_fs;
505 grp[DS] = (uint16_t)pcb->pcb_ds;
506 grp[ES] = (uint16_t)pcb->pcb_es;
507 } else {
508 grp[GS] = (uint16_t)rp->r_gs;
509 grp[FS] = (uint16_t)rp->r_fs;
510 grp[DS] = (uint16_t)rp->r_ds;
511 grp[ES] = (uint16_t)rp->r_es;
512 }
513 if (thisthread)
514 kpreempt_enable();
515 grp[EDI] = (greg32_t)rp->r_rdi;
516 grp[ESI] = (greg32_t)rp->r_rsi;
517 grp[EBP] = (greg32_t)rp->r_rbp;
518 grp[ESP] = 0;
519 grp[EBX] = (greg32_t)rp->r_rbx;
520 grp[EDX] = (greg32_t)rp->r_rdx;
521 grp[ECX] = (greg32_t)rp->r_rcx;
522 grp[EAX] = (greg32_t)rp->r_rax;
523 grp[TRAPNO] = (greg32_t)rp->r_trapno;
524 grp[ERR] = (greg32_t)rp->r_err;
525 grp[EIP] = (greg32_t)rp->r_rip;
526 grp[CS] = (uint16_t)rp->r_cs;
527 grp[EFL] = (greg32_t)rp->r_rfl;
528 grp[UESP] = (greg32_t)rp->r_rsp;
529 grp[SS] = (uint16_t)rp->r_ss;
530 }
531
532 void
533 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
534 {
535 mcontext_t *dmc = &dst->uc_mcontext;
536 const mcontext32_t *smc = &src->uc_mcontext;
537
538 bzero(dst, sizeof (*dst));
539 dst->uc_flags = src->uc_flags;
540 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
541
542 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
543
544 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
545 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
546 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
547
548 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
549 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
550 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
551 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
552 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
553 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
554 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
555 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
556 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
557 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
558 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
559 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
560 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
561 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
562 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
563 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
564 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
565 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
566
567 /*
568 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
569 * otherwise there is no guarantee that anything in fpregs is valid.
570 */
571 if (src->uc_flags & UC_FPU)
572 fpregset_32ton(&src->uc_mcontext.fpregs,
573 &dst->uc_mcontext.fpregs);
574 }
575
576 #endif /* _SYSCALL32_IMPL */
577
578 /*
579 * Return the user-level PC.
580 * If in a system call, return the address of the syscall trap.
581 */
582 greg_t
583 getuserpc()
584 {
585 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
586 uint32_t insn;
587
588 if (curthread->t_sysnum == 0)
589 return (upc);
590
591 /*
592 * We might've gotten here from sysenter (0xf 0x34),
593 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
594 *
595 * Go peek at the binary to figure it out..
596 */
597 if (fuword32((void *)(upc - 2), &insn) != -1 &&
598 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
599 return (upc - 2);
600 return (upc - 7);
601 }
602
603 /*
604 * Protect segment registers from non-user privilege levels and GDT selectors
605 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
606 * selector is non-null and not USER_CS/USER_DS, we make sure that the
607 * TI bit is set to point into the LDT and that the RPL is set to 3.
608 *
609 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
610 * also explicitly zero the top 16 bits since they may be coming from the
611 * user's address space via setcontext(2) or /proc.
612 *
613 * Note about null selector. When running on the hypervisor if we allow a
614 * process to set its %cs to null selector with RPL of 0 the hypervisor will
615 * crash the domain. If running on bare metal we would get a #gp fault and
616 * be able to kill the process and continue on. Therefore we make sure to
617 * force RPL to SEL_UPL even for null selector when setting %cs.
618 */
619
620 #if defined(IS_CS) || defined(IS_NOT_CS)
621 #error "IS_CS and IS_NOT_CS already defined"
622 #endif
623
624 #define IS_CS 1
625 #define IS_NOT_CS 0
626
627 /*ARGSUSED*/
628 static greg_t
629 fix_segreg(greg_t sr, int iscs, model_t datamodel)
630 {
631 switch (sr &= 0xffff) {
632
633 case 0:
634 if (iscs == IS_CS)
635 return (0 | SEL_UPL);
636 else
637 return (0);
638
639 #if defined(__amd64)
640 /*
641 * If lwp attempts to switch data model then force their
642 * code selector to be null selector.
643 */
644 case U32CS_SEL:
645 if (datamodel == DATAMODEL_NATIVE)
646 return (0 | SEL_UPL);
647 else
648 return (sr);
649
650 case UCS_SEL:
651 if (datamodel == DATAMODEL_ILP32)
652 return (0 | SEL_UPL);
653 #elif defined(__i386)
654 case UCS_SEL:
655 #endif
656 /*FALLTHROUGH*/
657 case UDS_SEL:
658 case LWPFS_SEL:
659 case LWPGS_SEL:
660 case SEL_UPL:
661 return (sr);
662 default:
663 break;
664 }
665
666 /*
667 * Force it into the LDT in ring 3 for 32-bit processes, which by
668 * default do not have an LDT, so that any attempt to use an invalid
669 * selector will reference the (non-existant) LDT, and cause a #gp
670 * fault for the process.
671 *
672 * 64-bit processes get the null gdt selector since they
673 * are not allowed to have a private LDT.
674 */
675 #if defined(__amd64)
676 if (datamodel == DATAMODEL_ILP32) {
677 return (sr | SEL_TI_LDT | SEL_UPL);
678 } else {
679 if (iscs == IS_CS)
680 return (0 | SEL_UPL);
681 else
682 return (0);
683 }
684
685 #elif defined(__i386)
686 return (sr | SEL_TI_LDT | SEL_UPL);
687 #endif
688 }
689
690 /*
691 * Set general registers.
692 */
693 void
694 setgregs(klwp_t *lwp, gregset_t grp)
695 {
696 struct regs *rp = lwptoregs(lwp);
697 model_t datamodel = lwp_getdatamodel(lwp);
698
699 #if defined(__amd64)
700 struct pcb *pcb = &lwp->lwp_pcb;
701 int thisthread = lwptot(lwp) == curthread;
702
703 if (datamodel == DATAMODEL_NATIVE) {
704
705 if (thisthread)
706 (void) save_syscall_args(); /* copy the args */
707
708 rp->r_rdi = grp[REG_RDI];
709 rp->r_rsi = grp[REG_RSI];
710 rp->r_rdx = grp[REG_RDX];
711 rp->r_rcx = grp[REG_RCX];
712 rp->r_r8 = grp[REG_R8];
713 rp->r_r9 = grp[REG_R9];
714 rp->r_rax = grp[REG_RAX];
715 rp->r_rbx = grp[REG_RBX];
716 rp->r_rbp = grp[REG_RBP];
717 rp->r_r10 = grp[REG_R10];
718 rp->r_r11 = grp[REG_R11];
719 rp->r_r12 = grp[REG_R12];
720 rp->r_r13 = grp[REG_R13];
721 rp->r_r14 = grp[REG_R14];
722 rp->r_r15 = grp[REG_R15];
723 rp->r_trapno = grp[REG_TRAPNO];
724 rp->r_err = grp[REG_ERR];
725 rp->r_rip = grp[REG_RIP];
726 /*
727 * Setting %cs or %ss to anything else is quietly but
728 * quite definitely forbidden!
729 */
730 rp->r_cs = UCS_SEL;
731 rp->r_ss = UDS_SEL;
732 rp->r_rsp = grp[REG_RSP];
733
734 if (thisthread)
735 kpreempt_disable();
736
737 pcb->pcb_ds = UDS_SEL;
738 pcb->pcb_es = UDS_SEL;
739
740 /*
741 * 64-bit processes -are- allowed to set their fsbase/gsbase
742 * values directly, but only if they're using the segment
743 * selectors that allow that semantic.
744 *
745 * (32-bit processes must use lwp_set_private().)
746 */
747 pcb->pcb_fsbase = grp[REG_FSBASE];
748 pcb->pcb_gsbase = grp[REG_GSBASE];
749 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
750 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
751
752 /*
753 * Ensure that we go out via update_sregs
754 */
755 pcb->pcb_rupdate = 1;
756 lwptot(lwp)->t_post_sys = 1;
757 if (thisthread)
758 kpreempt_enable();
759 #if defined(_SYSCALL32_IMPL)
760 } else {
761 rp->r_rdi = (uint32_t)grp[REG_RDI];
762 rp->r_rsi = (uint32_t)grp[REG_RSI];
763 rp->r_rdx = (uint32_t)grp[REG_RDX];
764 rp->r_rcx = (uint32_t)grp[REG_RCX];
765 rp->r_rax = (uint32_t)grp[REG_RAX];
766 rp->r_rbx = (uint32_t)grp[REG_RBX];
767 rp->r_rbp = (uint32_t)grp[REG_RBP];
768 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
769 rp->r_err = (uint32_t)grp[REG_ERR];
770 rp->r_rip = (uint32_t)grp[REG_RIP];
771
772 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
773 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
774
775 rp->r_rsp = (uint32_t)grp[REG_RSP];
776
777 if (thisthread)
778 kpreempt_disable();
779
780 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
781 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
782
783 /*
784 * (See fsbase/gsbase commentary above)
785 */
786 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
787 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
788
789 /*
790 * Ensure that we go out via update_sregs
791 */
792 pcb->pcb_rupdate = 1;
793 lwptot(lwp)->t_post_sys = 1;
794 if (thisthread)
795 kpreempt_enable();
796 #endif
797 }
798
799 /*
800 * Only certain bits of the flags register can be modified.
801 */
802 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
803 (grp[REG_RFL] & PSL_USERMASK);
804
805 #elif defined(__i386)
806
807 /*
808 * Only certain bits of the flags register can be modified.
809 */
810 grp[EFL] = (rp->r_efl & ~PSL_USERMASK) | (grp[EFL] & PSL_USERMASK);
811
812 /*
813 * Copy saved registers from user stack.
814 */
815 bcopy(grp, &rp->r_gs, sizeof (gregset_t));
816
817 rp->r_cs = fix_segreg(rp->r_cs, IS_CS, datamodel);
818 rp->r_ss = fix_segreg(rp->r_ss, IS_NOT_CS, datamodel);
819 rp->r_ds = fix_segreg(rp->r_ds, IS_NOT_CS, datamodel);
820 rp->r_es = fix_segreg(rp->r_es, IS_NOT_CS, datamodel);
821 rp->r_fs = fix_segreg(rp->r_fs, IS_NOT_CS, datamodel);
822 rp->r_gs = fix_segreg(rp->r_gs, IS_NOT_CS, datamodel);
823
824 #endif /* __i386 */
825 }
826
827 /*
828 * Determine whether eip is likely to have an interrupt frame
829 * on the stack. We do this by comparing the address to the
830 * range of addresses spanned by several well-known routines.
831 */
832 extern void _interrupt();
833 extern void _allsyscalls();
834 extern void _cmntrap();
835 extern void fakesoftint();
836
837 extern size_t _interrupt_size;
838 extern size_t _allsyscalls_size;
839 extern size_t _cmntrap_size;
840 extern size_t _fakesoftint_size;
841
842 /*
843 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
844 * Returns MIN(current stack depth, pcstack_limit).
845 */
846 int
847 getpcstack(pc_t *pcstack, int pcstack_limit)
848 {
849 struct frame *fp = (struct frame *)getfp();
850 struct frame *nextfp, *minfp, *stacktop;
851 int depth = 0;
852 int on_intr;
853 uintptr_t pc;
854
855 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
856 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
857 else
858 stacktop = (struct frame *)curthread->t_stk;
859 minfp = fp;
860
861 pc = ((struct regs *)fp)->r_pc;
862
863 while (depth < pcstack_limit) {
864 nextfp = (struct frame *)fp->fr_savfp;
865 pc = fp->fr_savpc;
866 if (nextfp <= minfp || nextfp >= stacktop) {
867 if (on_intr) {
868 /*
869 * Hop from interrupt stack to thread stack.
870 */
871 stacktop = (struct frame *)curthread->t_stk;
872 minfp = (struct frame *)curthread->t_stkbase;
873 on_intr = 0;
874 continue;
875 }
876 break;
877 }
878 pcstack[depth++] = (pc_t)pc;
879 fp = nextfp;
880 minfp = fp;
881 }
882 return (depth);
883 }
884
885 /*
886 * The following ELF header fields are defined as processor-specific
887 * in the V8 ABI:
888 *
889 * e_ident[EI_DATA] encoding of the processor-specific
890 * data in the object file
891 * e_machine processor identification
892 * e_flags processor-specific flags associated
893 * with the file
894 */
895
896 /*
897 * The value of at_flags reflects a platform's cpu module support.
898 * at_flags is used to check for allowing a binary to execute and
899 * is passed as the value of the AT_FLAGS auxiliary vector.
900 */
901 int at_flags = 0;
902
903 /*
904 * Check the processor-specific fields of an ELF header.
905 *
906 * returns 1 if the fields are valid, 0 otherwise
907 */
908 /*ARGSUSED2*/
909 int
910 elfheadcheck(
911 unsigned char e_data,
912 Elf32_Half e_machine,
913 Elf32_Word e_flags)
914 {
915 if (e_data != ELFDATA2LSB)
916 return (0);
917 #if defined(__amd64)
918 if (e_machine == EM_AMD64)
919 return (1);
920 #endif
921 return (e_machine == EM_386);
922 }
923
924 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
925 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
926 #if defined(_SYSCALL32_IMPL)
927 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
928 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
929 #endif
930
931 /*
932 * Gather information about the processor and place it into auxv_hwcap
933 * so that it can be exported to the linker via the aux vector.
934 *
935 * We use this seemingly complicated mechanism so that we can ensure
936 * that /etc/system can be used to override what the system can or
937 * cannot discover for itself.
938 */
939 void
940 bind_hwcap(void)
941 {
942 uint_t cpu_hwcap_flags = cpuid_pass4(NULL);
943
944 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags) &
945 ~auxv_hwcap_exclude;
946
947 #if defined(__amd64)
948 /*
949 * On AMD processors, sysenter just doesn't work at all
950 * when the kernel is in long mode. On IA-32e processors
951 * it does, but there's no real point in all the alternate
952 * mechanism when syscall works on both.
953 *
954 * Besides, the kernel's sysenter handler is expecting a
955 * 32-bit lwp ...
956 */
957 auxv_hwcap &= ~AV_386_SEP;
958 #else
959 /*
960 * 32-bit processes can -always- use the lahf/sahf instructions
961 */
962 auxv_hwcap |= AV_386_AHF;
963 #endif
964
965 if (auxv_hwcap_include || auxv_hwcap_exclude)
966 cmn_err(CE_CONT, "?user ABI extensions: %b\n",
967 auxv_hwcap, FMT_AV_386);
968
969 #if defined(_SYSCALL32_IMPL)
970 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags) &
971 ~auxv_hwcap32_exclude;
972
973 #if defined(__amd64)
974 /*
975 * If this is an amd64 architecture machine from Intel, then
976 * syscall -doesn't- work in compatibility mode, only sysenter does.
977 *
978 * Sigh.
979 */
980 if (!cpuid_syscall32_insn(NULL))
981 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
982
983 /*
984 * 32-bit processes can -always- use the lahf/sahf instructions
985 */
986 auxv_hwcap32 |= AV_386_AHF;
987 #endif
988
989 if (auxv_hwcap32_include || auxv_hwcap32_exclude)
990 cmn_err(CE_CONT, "?32-bit user ABI extensions: %b\n",
991 auxv_hwcap32, FMT_AV_386);
992 #endif
993 }
994
995 /*
996 * sync_icache() - this is called
997 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
998 * this is a nop.
999 */
1000 /* ARGSUSED */
1001 void
1002 sync_icache(caddr_t addr, uint_t len)
1003 {
1004 /* Do nothing for now */
1005 }
1006
1007 /*ARGSUSED*/
1008 void
1009 sync_data_memory(caddr_t va, size_t len)
1010 {
1011 /* Not implemented for this platform */
1012 }
1013
1014 int
1015 __ipltospl(int ipl)
1016 {
1017 return (ipltospl(ipl));
1018 }
1019
1020 /*
1021 * The panic code invokes panic_saveregs() to record the contents of a
1022 * regs structure into the specified panic_data structure for debuggers.
1023 */
1024 void
1025 panic_saveregs(panic_data_t *pdp, struct regs *rp)
1026 {
1027 panic_nv_t *pnv = PANICNVGET(pdp);
1028
1029 struct cregs creg;
1030
1031 getcregs(&creg);
1032
1033 #if defined(__amd64)
1034 PANICNVADD(pnv, "rdi", rp->r_rdi);
1035 PANICNVADD(pnv, "rsi", rp->r_rsi);
1036 PANICNVADD(pnv, "rdx", rp->r_rdx);
1037 PANICNVADD(pnv, "rcx", rp->r_rcx);
1038 PANICNVADD(pnv, "r8", rp->r_r8);
1039 PANICNVADD(pnv, "r9", rp->r_r9);
1040 PANICNVADD(pnv, "rax", rp->r_rax);
1041 PANICNVADD(pnv, "rbx", rp->r_rbx);
1042 PANICNVADD(pnv, "rbp", rp->r_rbp);
1043 PANICNVADD(pnv, "r10", rp->r_r10);
1044 PANICNVADD(pnv, "r10", rp->r_r10);
1045 PANICNVADD(pnv, "r11", rp->r_r11);
1046 PANICNVADD(pnv, "r12", rp->r_r12);
1047 PANICNVADD(pnv, "r13", rp->r_r13);
1048 PANICNVADD(pnv, "r14", rp->r_r14);
1049 PANICNVADD(pnv, "r15", rp->r_r15);
1050 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
1051 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
1052 PANICNVADD(pnv, "ds", rp->r_ds);
1053 PANICNVADD(pnv, "es", rp->r_es);
1054 PANICNVADD(pnv, "fs", rp->r_fs);
1055 PANICNVADD(pnv, "gs", rp->r_gs);
1056 PANICNVADD(pnv, "trapno", rp->r_trapno);
1057 PANICNVADD(pnv, "err", rp->r_err);
1058 PANICNVADD(pnv, "rip", rp->r_rip);
1059 PANICNVADD(pnv, "cs", rp->r_cs);
1060 PANICNVADD(pnv, "rflags", rp->r_rfl);
1061 PANICNVADD(pnv, "rsp", rp->r_rsp);
1062 PANICNVADD(pnv, "ss", rp->r_ss);
1063 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
1064 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
1065 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
1066 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
1067 #elif defined(__i386)
1068 PANICNVADD(pnv, "gs", (uint32_t)rp->r_gs);
1069 PANICNVADD(pnv, "fs", (uint32_t)rp->r_fs);
1070 PANICNVADD(pnv, "es", (uint32_t)rp->r_es);
1071 PANICNVADD(pnv, "ds", (uint32_t)rp->r_ds);
1072 PANICNVADD(pnv, "edi", (uint32_t)rp->r_edi);
1073 PANICNVADD(pnv, "esi", (uint32_t)rp->r_esi);
1074 PANICNVADD(pnv, "ebp", (uint32_t)rp->r_ebp);
1075 PANICNVADD(pnv, "esp", (uint32_t)rp->r_esp);
1076 PANICNVADD(pnv, "ebx", (uint32_t)rp->r_ebx);
1077 PANICNVADD(pnv, "edx", (uint32_t)rp->r_edx);
1078 PANICNVADD(pnv, "ecx", (uint32_t)rp->r_ecx);
1079 PANICNVADD(pnv, "eax", (uint32_t)rp->r_eax);
1080 PANICNVADD(pnv, "trapno", (uint32_t)rp->r_trapno);
1081 PANICNVADD(pnv, "err", (uint32_t)rp->r_err);
1082 PANICNVADD(pnv, "eip", (uint32_t)rp->r_eip);
1083 PANICNVADD(pnv, "cs", (uint32_t)rp->r_cs);
1084 PANICNVADD(pnv, "eflags", (uint32_t)rp->r_efl);
1085 PANICNVADD(pnv, "uesp", (uint32_t)rp->r_uesp);
1086 PANICNVADD(pnv, "ss", (uint32_t)rp->r_ss);
1087 PANICNVADD(pnv, "gdt", creg.cr_gdt);
1088 PANICNVADD(pnv, "idt", creg.cr_idt);
1089 #endif /* __i386 */
1090
1091 PANICNVADD(pnv, "ldt", creg.cr_ldt);
1092 PANICNVADD(pnv, "task", creg.cr_task);
1093 PANICNVADD(pnv, "cr0", creg.cr_cr0);
1094 PANICNVADD(pnv, "cr2", creg.cr_cr2);
1095 PANICNVADD(pnv, "cr3", creg.cr_cr3);
1096 if (creg.cr_cr4)
1097 PANICNVADD(pnv, "cr4", creg.cr_cr4);
1098
1099 PANICNVSET(pdp, pnv);
1100 }
1101
1102 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
1103
1104 #if !defined(__amd64)
1105
1106 /*
1107 * Given a return address (%eip), determine the likely number of arguments
1108 * that were pushed on the stack prior to its execution. We do this by
1109 * expecting that a typical call sequence consists of pushing arguments on
1110 * the stack, executing a call instruction, and then performing an add
1111 * on %esp to restore it to the value prior to pushing the arguments for
1112 * the call. We attempt to detect such an add, and divide the addend
1113 * by the size of a word to determine the number of pushed arguments.
1114 *
1115 * If we do not find such an add, we punt and return TR_ARG_MAX. It is not
1116 * possible to reliably determine if a function took no arguments (i.e. was
1117 * void) because assembler routines do not reliably perform an add on %esp
1118 * immediately upon returning (eg. _sys_call()), so returning TR_ARG_MAX is
1119 * safer than returning 0.
1120 */
1121 static ulong_t
1122 argcount(uintptr_t eip)
1123 {
1124 const uint8_t *ins = (const uint8_t *)eip;
1125 ulong_t n;
1126
1127 enum {
1128 M_MODRM_ESP = 0xc4, /* Mod/RM byte indicates %esp */
1129 M_ADD_IMM32 = 0x81, /* ADD imm32 to r/m32 */
1130 M_ADD_IMM8 = 0x83 /* ADD imm8 to r/m32 */
1131 };
1132
1133 if (eip < KERNELBASE || ins[1] != M_MODRM_ESP)
1134 return (TR_ARG_MAX);
1135
1136 switch (ins[0]) {
1137 case M_ADD_IMM32:
1138 n = ins[2] + (ins[3] << 8) + (ins[4] << 16) + (ins[5] << 24);
1139 break;
1140
1141 case M_ADD_IMM8:
1142 n = ins[2];
1143 break;
1144
1145 default:
1146 return (TR_ARG_MAX);
1147 }
1148
1149 n /= sizeof (long);
1150 return (MIN(n, TR_ARG_MAX));
1151 }
1152
1153 #endif /* !__amd64 */
1154
1155 /*
1156 * Print a stack backtrace using the specified frame pointer. We delay two
1157 * seconds before continuing, unless this is the panic traceback.
1158 * If we are in the process of panicking, we also attempt to write the
1159 * stack backtrace to a staticly assigned buffer, to allow the panic
1160 * code to find it and write it in to uncompressed pages within the
1161 * system crash dump.
1162 * Note that the frame for the starting stack pointer value is omitted because
1163 * the corresponding %eip is not known.
1164 */
1165
1166 extern char *dump_stack_scratch;
1167
1168 #if defined(__amd64)
1169
1170 void
1171 traceback(caddr_t fpreg)
1172 {
1173 struct frame *fp = (struct frame *)fpreg;
1174 struct frame *nextfp;
1175 uintptr_t pc, nextpc;
1176 ulong_t off;
1177 char args[TR_ARG_MAX * 2 + 16], *sym;
1178 uint_t offset = 0;
1179 uint_t next_offset = 0;
1180 char stack_buffer[1024];
1181
1182 if (!panicstr)
1183 printf("traceback: %%fp = %p\n", (void *)fp);
1184
1185 if (panicstr && !dump_stack_scratch) {
1186 printf("Warning - stack not written to the dump buffer\n");
1187 }
1188
1189 fp = (struct frame *)plat_traceback(fpreg);
1190 if ((uintptr_t)fp < KERNELBASE)
1191 goto out;
1192
1193 pc = fp->fr_savpc;
1194 fp = (struct frame *)fp->fr_savfp;
1195
1196 while ((uintptr_t)fp >= KERNELBASE) {
1197 /*
1198 * XX64 Until port is complete tolerate 8-byte aligned
1199 * frame pointers but flag with a warning so they can
1200 * be fixed.
1201 */
1202 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
1203 if (((uintptr_t)fp & (8 - 1)) == 0) {
1204 printf(" >> warning! 8-byte"
1205 " aligned %%fp = %p\n", (void *)fp);
1206 } else {
1207 printf(
1208 " >> mis-aligned %%fp = %p\n", (void *)fp);
1209 break;
1210 }
1211 }
1212
1213 args[0] = '\0';
1214 nextpc = (uintptr_t)fp->fr_savpc;
1215 nextfp = (struct frame *)fp->fr_savfp;
1216 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1217 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1218 mod_containing_pc((caddr_t)pc), sym, off, args);
1219 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1220 "%s:%s+%lx (%s) | ",
1221 mod_containing_pc((caddr_t)pc), sym, off, args);
1222 } else {
1223 printf("%016lx %lx (%s)\n",
1224 (uintptr_t)fp, pc, args);
1225 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1226 "%lx (%s) | ", pc, args);
1227 }
1228
1229 if (panicstr && dump_stack_scratch) {
1230 next_offset = offset + strlen(stack_buffer);
1231 if (next_offset < STACK_BUF_SIZE) {
1232 bcopy(stack_buffer, dump_stack_scratch + offset,
1233 strlen(stack_buffer));
1234 offset = next_offset;
1235 } else {
1236 /*
1237 * In attempting to save the panic stack
1238 * to the dumpbuf we have overflowed that area.
1239 * Print a warning and continue to printf the
1240 * stack to the msgbuf
1241 */
1242 printf("Warning: stack in the dump buffer"
1243 " may be incomplete\n");
1244 offset = next_offset;
1245 }
1246 }
1247
1248 pc = nextpc;
1249 fp = nextfp;
1250 }
1251 out:
1252 if (!panicstr) {
1253 printf("end of traceback\n");
1254 DELAY(2 * MICROSEC);
1255 } else if (dump_stack_scratch) {
1256 dump_stack_scratch[offset] = '\0';
1257 }
1258 }
1259
1260 #elif defined(__i386)
1261
1262 void
1263 traceback(caddr_t fpreg)
1264 {
1265 struct frame *fp = (struct frame *)fpreg;
1266 struct frame *nextfp, *minfp, *stacktop;
1267 uintptr_t pc, nextpc;
1268 uint_t offset = 0;
1269 uint_t next_offset = 0;
1270 char stack_buffer[1024];
1271
1272 cpu_t *cpu;
1273
1274 /*
1275 * args[] holds TR_ARG_MAX hex long args, plus ", " or '\0'.
1276 */
1277 char args[TR_ARG_MAX * 2 + 8], *p;
1278
1279 int on_intr;
1280 ulong_t off;
1281 char *sym;
1282
1283 if (!panicstr)
1284 printf("traceback: %%fp = %p\n", (void *)fp);
1285
1286 if (panicstr && !dump_stack_scratch) {
1287 printf("Warning - stack not written to the dumpbuf\n");
1288 }
1289
1290 /*
1291 * If we are panicking, all high-level interrupt information in
1292 * CPU was overwritten. panic_cpu has the correct values.
1293 */
1294 kpreempt_disable(); /* prevent migration */
1295
1296 cpu = (panicstr && CPU->cpu_id == panic_cpu.cpu_id)? &panic_cpu : CPU;
1297
1298 if ((on_intr = CPU_ON_INTR(cpu)) != 0)
1299 stacktop = (struct frame *)(cpu->cpu_intr_stack + SA(MINFRAME));
1300 else
1301 stacktop = (struct frame *)curthread->t_stk;
1302
1303 kpreempt_enable();
1304
1305 fp = (struct frame *)plat_traceback(fpreg);
1306 if ((uintptr_t)fp < KERNELBASE)
1307 goto out;
1308
1309 minfp = fp; /* Baseline minimum frame pointer */
1310 pc = fp->fr_savpc;
1311 fp = (struct frame *)fp->fr_savfp;
1312
1313 while ((uintptr_t)fp >= KERNELBASE) {
1314 ulong_t argc;
1315 long *argv;
1316
1317 if (fp <= minfp || fp >= stacktop) {
1318 if (on_intr) {
1319 /*
1320 * Hop from interrupt stack to thread stack.
1321 */
1322 stacktop = (struct frame *)curthread->t_stk;
1323 minfp = (struct frame *)curthread->t_stkbase;
1324 on_intr = 0;
1325 continue;
1326 }
1327 break; /* we're outside of the expected range */
1328 }
1329
1330 if ((uintptr_t)fp & (STACK_ALIGN - 1)) {
1331 printf(" >> mis-aligned %%fp = %p\n", (void *)fp);
1332 break;
1333 }
1334
1335 nextpc = fp->fr_savpc;
1336 nextfp = (struct frame *)fp->fr_savfp;
1337 argc = argcount(nextpc);
1338 argv = (long *)((char *)fp + sizeof (struct frame));
1339
1340 args[0] = '\0';
1341 p = args;
1342 while (argc-- > 0 && argv < (long *)stacktop) {
1343 p += snprintf(p, args + sizeof (args) - p,
1344 "%s%lx", (p == args) ? "" : ", ", *argv++);
1345 }
1346
1347 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1348 printf("%08lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1349 mod_containing_pc((caddr_t)pc), sym, off, args);
1350 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1351 "%s:%s+%lx (%s) | ",
1352 mod_containing_pc((caddr_t)pc), sym, off, args);
1353
1354 } else {
1355 printf("%08lx %lx (%s)\n",
1356 (uintptr_t)fp, pc, args);
1357 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1358 "%lx (%s) | ", pc, args);
1359
1360 }
1361
1362 if (panicstr && dump_stack_scratch) {
1363 next_offset = offset + strlen(stack_buffer);
1364 if (next_offset < STACK_BUF_SIZE) {
1365 bcopy(stack_buffer, dump_stack_scratch + offset,
1366 strlen(stack_buffer));
1367 offset = next_offset;
1368 } else {
1369 /*
1370 * In attempting to save the panic stack
1371 * to the dumpbuf we have overflowed that area.
1372 * Print a warning and continue to printf the
1373 * stack to the msgbuf
1374 */
1375 printf("Warning: stack in the dumpbuf"
1376 " may be incomplete\n");
1377 offset = next_offset;
1378 }
1379 }
1380
1381 minfp = fp;
1382 pc = nextpc;
1383 fp = nextfp;
1384 }
1385 out:
1386 if (!panicstr) {
1387 printf("end of traceback\n");
1388 DELAY(2 * MICROSEC);
1389 } else if (dump_stack_scratch) {
1390 dump_stack_scratch[offset] = '\0';
1391 }
1392
1393 }
1394
1395 #endif /* __i386 */
1396
1397 /*
1398 * Generate a stack backtrace from a saved register set.
1399 */
1400 void
1401 traceregs(struct regs *rp)
1402 {
1403 traceback((caddr_t)rp->r_fp);
1404 }
1405
1406 void
1407 exec_set_sp(size_t stksize)
1408 {
1409 klwp_t *lwp = ttolwp(curthread);
1410
1411 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1412 }
1413
1414 hrtime_t
1415 gethrtime_waitfree(void)
1416 {
1417 return (dtrace_gethrtime());
1418 }
1419
1420 hrtime_t
1421 gethrtime(void)
1422 {
1423 return (gethrtimef());
1424 }
1425
1426 hrtime_t
1427 gethrtime_unscaled(void)
1428 {
1429 return (gethrtimeunscaledf());
1430 }
1431
1432 void
1433 scalehrtime(hrtime_t *hrt)
1434 {
1435 scalehrtimef(hrt);
1436 }
1437
1438 uint64_t
1439 unscalehrtime(hrtime_t nsecs)
1440 {
1441 return (unscalehrtimef(nsecs));
1442 }
1443
1444 void
1445 gethrestime(timespec_t *tp)
1446 {
1447 gethrestimef(tp);
1448 }
1449
1450 #if defined(__amd64)
1451 /*
1452 * Part of the implementation of hres_tick(); this routine is
1453 * easier in C than assembler .. called with the hres_lock held.
1454 *
1455 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1456 */
1457
1458 #include <sys/time.h>
1459 #include <sys/machlock.h>
1460
1461 extern int one_sec;
1462 extern int max_hres_adj;
1463
1464 void
1465 __adj_hrestime(void)
1466 {
1467 long long adj;
1468
1469 if (hrestime_adj == 0)
1470 adj = 0;
1471 else if (hrestime_adj > 0) {
1472 if (hrestime_adj < max_hres_adj)
1473 adj = hrestime_adj;
1474 else
1475 adj = max_hres_adj;
1476 } else {
1477 if (hrestime_adj < -max_hres_adj)
1478 adj = -max_hres_adj;
1479 else
1480 adj = hrestime_adj;
1481 }
1482
1483 timedelta -= adj;
1484 hrestime_adj = timedelta;
1485 hrestime.tv_nsec += adj;
1486
1487 while (hrestime.tv_nsec >= NANOSEC) {
1488 one_sec++;
1489 hrestime.tv_sec++;
1490 hrestime.tv_nsec -= NANOSEC;
1491 }
1492 }
1493 #endif
1494
1495 /*
1496 * Wrapper functions to maintain backwards compability
1497 */
1498 int
1499 xcopyin(const void *uaddr, void *kaddr, size_t count)
1500 {
1501 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1502 }
1503
1504 int
1505 xcopyout(const void *kaddr, void *uaddr, size_t count)
1506 {
1507 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1508 }